Intel recently introduced its glass substrate technology at the APJ Packaging Roundtable technical event and said, "We plan to introduce quartz glass substrates in the second half of this decade.". We expect this to continue to improve semiconductor performance.
As semiconductor circuits become more complex and thinner, the semiconductor industry is increasingly demanding new types of substrates. Plastic substrates are already problematic because their rough surfaces can negatively affect the inherent performance of ultra-fine circuits.
As an alternative, glass substrates have emerged. These substrates, made of glass, have a smoother surface than plastic substrates and may double the performance of high-performance chips when mounted on them. The baseplate can also be more than a quarter thinner than previous designs, helping to reduce the mounting area. Power consumption can also be halved compared to conventional models. Although the commercialization of glass substrates may take some time, it is predicted that once realized, it will become a new game changer in the substrate industry.
Glass, is expected to take over? The Japanese Dai Nippon Printing (DNP)
has unveiled a new development in semiconductor packaging, the glass-core carrier plate (GCS: Glass Core Substrate), which is said to solve many of the problems associated with ABF.
DNP claims that its HDI carrier plate with a glass core has superior performance compared to organic resin-based carrier plates. According to Dai Nippon, finer pitch and therefore extremely dense wiring can be achieved using a glass core carrier plate (GCS), which is stiffer and less prone to expansion due to high temperatures. The schematic shown by DNP even omits the fine pitch carrier plate from the package altogether, suggesting that this part may no longer be needed.
DNP also said in the report that its glass-core carrier plate can provide high through-glass via (TGV) density with high aspect ratio (compatible with FPS). In this case, the aspect ratio is the ratio between the thickness of the glass and the diameter of the through-hole. As the number and proportion of vias increase, the processing of the carrier plate becomes more and more difficult, and it becomes more challenging to maintain rigidity.
From the introduction of DNP, it can be seen that the glass carrier plate developed by DNP has an aspect ratio of 9 and ensures adhesion to achieve fine pitch compatible wiring. Because there are few GCS thickness restrictions, there is a lot of freedom in maintaining a balance between thickness, warping, stiffness and smoothness, the company said. "We also have new proprietary manufacturing methods to enhance the adhesion between glass and metal, which is difficult to achieve with traditional technology, which also helps them achieve fine spacing and high reliability." The DNP also stressed.
In addition to DNP, Absolics, a subsidiary of SK Group in Korea, is also optimistic about the opportunities brought by glass. Because they believe that glass has high heat resistance, they regard it as the innovator of semiconductor packaging. Absolics said that as the performance improvement of micro-processing has reached its limit, the semiconductor industry is actively utilizing heterogeneous packaging, but existing semiconductor carriers must be connected to semiconductor chips through intermediate carriers called silicon interposers, while glass carriers with built-in passive components can integrate more chips in the same size and reduce power consumption by half. It is worth mentioning that Absolics has also received investment from Applied Materials, a major American equipment manufacturer.
In addition, Corning, a big glass manufacturer, is also optimistic about the opportunities of glass in the carrier plate. New initiatives in semiconductor packaging have created a demand for new material solutions,
they wrote in a paper. Great efforts have been made to extend the interposer technology for 3D-IC stacking. A variety of solutions are being developed to address some of these needs, including traditional interposers using a variety of commonly used materials, as well as fan-out wafer level packaging (FOWLP), which has become a common consideration in attempts to achieve low cost.
In addition, the proliferation of mobile devices and the Internet of Things (IoT) has led to an increasing demand for RF communications. These requirements include the introduction of more frequency bands, smaller/thinner package sizes, and the need to conserve power to extend battery life when new features are introduced. Glass has proven to be an excellent solution to these challenges because it has many properties that support these efforts, including high resistivity and low electrical loss, low or adjustable dielectric constant, and adjustable coefficient of thermal expansion (CTE).
Corning said that one of the important challenges of 3D IC stacking is reliability due to CTE mismatch, and glass provides an excellent opportunity to manage the warping of 3D-IC stacks while optimizing CTE. The following diagram illustrates the challenges of stacking carrier boards with multiple CTEs in an interposer application. Wherein the left figure schematically shows a Si chip mounted on a Si interposer and then mounted on an organic carrier board. When the carrier board is subjected to temperature cycling, a CTE mismatch can lead to failure.
However, if a glass interposer with a CTE between glass and organic is used instead of a Si interposer, this warpage can be better managed and reliability can be improved, as demonstrated by the work of the Packaging Research Center (PRC) at Georgia Tech.
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